1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit and an ESD device thereof, and more particularly, to an electrostatic discharge (ESD) protection circuit and an ESD device thereof using a silicon-controlled rectifier (SCR) to discharge ESD current.
2. Description of the Prior Art
Electrostatic discharge (ESD) represents one of the main threats to reliability in semiconductor products, especially in scaled-down CMOS technologies. Due to low breakdown voltage of thinner gate oxide in deep-submicron CMOS technologies, an efficient ESD protection circuit must be designed and placed on every input pad to clamp the overstress voltage across the gate oxide of the internal circuit. However, the ESD protection circuit inevitably introduces negative impacts to RF performance due to their parasitic capacitance. As the operating frequency of RF circuits increases, performance degradation due to ESD protection circuits becomes more serious. Silicon-controlled rectifier (SCR) is demonstrated to be suitable for ESD protection design for RF ICs, because it has both high ESD robustness and low parasitic capacitance under a small layout area.
Referring to FIG. 1 and FIG. 2, FIG. 1 is a schematic diagram illustrating a SCR according to prior art, and FIG. 2 is a schematic diagram illustrating an I-V curve of the SCR. As shown in FIG. 1, the SCR 10 is electrically connected between an input/output (I/O) pad 12 and a ground 14, and has a P-type substrate 16, a N-type well 18 disposed in the P-type substrate 16, a first P-type doped region 20 and a first N-type doped region 22 disposed in the N-type well 18, and a second N-type doped region 24 and a second P-type doped region 26 disposed in the P-type substrate 16. The first P-type doped region 20 and the first N-type doped region 22 are electrically connected to the I/O pad 12, and the second N-type doped region 24 and the second P-type doped region 26 are electrically connected to the ground 14. The SCR 10 provides a discharge path 28 composed of a PNPN structure, and the PNPN structure is formed by the first P-type doped region 20, the N-well 18, the P-type substrate 16 and the second N-type doped region 24 in sequence. As shown in FIG. 2, the SCR 10 has a trigger voltage Vtr and a holding voltage VH. When an ESD event occurs on the I/O pad 12, and an ESD voltage is higher than the trigger voltage Vtr, the SCR 10 is triggered on and into a latch-up state. In the latch-up state, the holding voltage VH across the SCR 10 is lower than the trigger voltage Vtr, and the ESD current can be discharged through the discharge path 28. When the ESD event does not occur, the operating voltage inputted to the I/O pad is not larger than the trigger voltage Vtr, and the SCR cannot be triggered on. Therefore, the SCR is in off state, and an internal circuit connected to the I/O pad 12 can operate normally.
However, during normal operation of the internal circuit, some noise is generated, and at the same time, the operating voltage inputted to the I/O pad is larger than the trigger voltage. Thus, the SCR will be triggered on and into the latch-up state, and the discharge path is opened during normal operation. Accordingly, leakage current passing the discharge path is generated, and the internal circuit cannot operate normally. Therefore, to solve the problem of the SCR being triggered on by the noise during normal operation is an important objective for industry.